(a) Technical Field
The present disclosure relates to a memory controller, and more specifically to a device and method which can stably fetch data from a memory controller.
(b) Discussion of the Related Art
Large scale integrated circuits are manufactured using minimum feature size technologies, and these technologies cause considerable variations of device characteristics due to process, voltage and temperature PVT variations. The PVT variations can cause variations in rise and fall times of transmission signals, which in turn result in signal delays. Thus, it is beneficial to be able to adjust signal delay in various routes or paths in an integrated circuit so variations in signal delay caused by PVT can be minimized.
FIG. 1 is a block diagram showing a conventional flash memory controller.
The memory controller illustrated in the FIG. 1 controls a NAND flash memory device, and comprises a central processing unit CPU 120, RAM 140 operating as a buffer memory, and a flash interface controller 160. The central processing unit 120 is configured to control the overall operations of the memory controller. For example, the central processing unit 120 controls the flash interface controller 160 so that a read/write operation of the flash memory 200 is carried out based on a command from a host. The RAM 140 temporarily stores data from the host at a write operation and data read out from the flash memory 200 at a read operation. The RAM 140 may be embodied, for example, with SRAM. However, the RAM 140 can also be embodied using other RAMs such as DRAM, PRAM, MRAM, and the like. The flash interface controller 160 controls the read/write operation of the flash memory 200 based on the control of the central processing unit 120. For example, when the write operation is being performed, the flash interface controller 160 transmits temporarily stored data in the RAM 140 and a write command to the flash memory 200 in accordance with a given timing. When the read operation is being performed, the flash interface controller 160 transmits a read command to the flash memory 200 in accordance with a given timing, and transmits data from the flash memory 200 to the RAM 140 after a period of time has elapsed. The flash memory 200 has a command/address/data multiplexed 10 structure where addresses, data, and command are provided through a data path.
FIG. 2 is a block diagram showing a part of the flash interface controller illustrated in FIG. 1.
Referring to FIG. 2, the flash interface controller 160 comprises a flash control block 162 and a data latch block 164. The flash control block 162 is operated in synchronization with a system clock signal SCLK, and is configured to generate control signals (e.g., CLE, CEB WEB, REB, ALE, etc.) that are to be applied to the flash memory 200 in accordance with a given timing at respective modes of operation. The flash control block 162 comprises an output enable signal generator 162a, which generates a clock signal O_REB in synchronization with the system clock signal SCLK The generated clock signal O_REB is outputted as the output enable signal REB to the flash memory 200 through a buffer 101 connected to a pad PD1. Although only the signal generator 162a for generating the O_REB signal is illustrated in the flash control block 162, signal generators for generating other control signals are also provided in the flash control block 162.
During a write operation, the data latch block 164 receives data O_OUT (e.g., it is provided from RAM 140 in FIG. 1) to be transmitted to the flash memory 200, and outputs the inputted data to the flash memory 200 through a buffer 102 connected to a pad PD2. During a read operation, the data latch block 164 latches data DQ transferred from the flash memory 200 through a buffer 103 connected to the pad PD2, and outputs the latched data O_DIN to the RAM 140 in FIG. 1. The data latch block 164 comprises a data output latch 164a and a data input latch 164b. For convenience of illustration, a data latch structure for inputting/outputting only 1-bit data is illustrated in the figures. However a data latch structure for inputting/outputting more than one data bit may also be used. The data output latch 164a latches/outputs data in synchronization with the system clock signal SCLK at the write operation, while the data input latch 164b latches data in synchronization with the clock signal O_REB from the output enable signal generator 162a at the read operation.
To read data from the flash memory 200, as shown in FIG. 3, the flash control block 162 transmits a read command and an address to the flash memory 200 in accordance with a predetermined timing. After a given time, the flash control block 162 generates the clock signal O_REB as an output enable signal REB in response to interrupt information (e.g., R/>B) from the flash memory 200. The flash memory 200 sequentially outputs data (e.g., page data) in given units (e.g., ×8, ×16, ×32, etc.) in response to the output enable signal REB. The data latch block 164 of the flash interface controller 160 latches data transferred from the flash memory 200 through the buffer 103 in response to the O_REB signal. The data input latch 164b latches data from the flash memory 200 directly using the O_REB signal from the signal generator 162a. As also seen in FIG. 2 the O_REB signal is transmitted to the flash memory 200 through a signal route, which includes the buffer 101, the pad PD1 and is transmitted directly to the data input latch 164b. The O_REB signal is transmitted to the flash memory 200 and the data input latch 164a through different signal routes, respectively. A signal delay generated by such signal routes varies based on PVT variations. This means that delay of the output enable signal REB transmitted to the flash memory 200 can be different from delay of the output enable signal O_REB to the data input latch 164b based on PVT variations. The varying delays make it difficult to stably latch data from the flash memory 200. Thus there is a need for a device and a method which can stably fetch data from a memory controller.